A processor having high processing speed has been required corresponding to requirements for higher speed and higher functions in high speed processing device. The Very Long Instruction Word (which is abbreviated as VLIW) is one of techniques for enhancing the speed of processors. In a processor applying the VLIW technique, order relations between instruction words or data dependency relations are analyzed in compiling programs to extract a group of instruction words which can be performed simultaneously. Based on such processing, high performance is realized by simultaneous performing of a plurality of instruction words without a run-time overhead.
With to the VLIW technique, hardware can be simplified, cache can be easily increased, and a clock frequency can be easily increased. Further, it is required for a VLIW processor to merely process read-in instruction directly. For example, in hardware applying a superscalar technique and so on, a circuit for extracting instructions which can be performed simultaneously is required. However, in the VLIW processor, such a circuit is not required. In this manner, the VLIW processor does not depend on a circuit having a complex configuration, so that it can be applicable to a low power consumption type embedded system.
Further, a VLIW processor can be perform a very long instruction composed of a plurality of instruction words (calculation, load, and so on). Moreover, as described above, in a VLIW processor, the processing for extracting instruction words which are performed simultaneously can be carried out by only one time processing of compiling, so that the overhead accompanied with parallel processing is very small. On the other hand, in the VLIW processor, when the number of instruction words which can be performed simultaneously is not reach the maximum number of simultaneously performable instruction words, it is required to insert an invalid calculation instruction word in the very long instruction, so that there is a case where the density of the instruction code decreases.
As a technique for preventing the decrease of the density of an instruction code, a related technique disclosed in Japanese Patent Application Publication JP-P2004-078627A is known. In the related technique, as shown in FIG. 1, by adding a successive instruction prescription bit α which indicates whether the successive instruction word is simultaneously performed for each of the instruction words to a very long instruction P composed of an instruction word group Ik (k≧1), the number of instruction words consisting the very long instruction P can be able to determine, so that the very long instruction P whose length is variable is realized. In this manner, invalid calculation instruction word which is not required is eliminated from the very long instruction P, so that the decrease of the density of an instruction code can be prevented.
In the information processing device for the VLIW instruction described in the above related technique, the number of instruction words is determined in accordance with the successive instruction prescription bit included in the very long instruction. Therefore, in the information processing device for the VLIW instruction described in the above related technique, it is required to fetch instruction words whose number is equal to the maximum number of simultaneously performable instruction words necessarily, and to check successive instruction prescription bits added to all of the instruction words. Therefore, in the information processing device for the VLIW instruction described in the above related technique, when the number of instruction words which are performed simultaneously does not reach the maximum number of simultaneously per formable instruction words, unnecessary instruction words are also fetched. Further, in a general VLIW processor, an average number of instruction words performed simultaneously is about half of the maximum number of the simultaneously performable instruction words. As a result, about a half of fetch of a very long instruction performed on the information processing device for the VLIW instruction described in the above related technique becomes unnecessary operation, so that it causes an invalid power consumption.